qdma

1、EDMA3(theenhanceddirectmemoryaccess)controller’sprimarypurpois

torviceur-prigrammeddatatransfersbetweentwomemory-mapped

slaveendpointsonthedevice.

2、EDMA3includestwoparts:EDMA3CC(EDMA3channelcontroller)&

EDMA3TC(EDMA3transfercontroller).

1)EDMA3CCincludesparameterRAM(PaRAM),channelcontrolregisters,

itstransferrequest(TR)tothetransfer

controller.

2)Itincludestwochanneltypes:DMAchannels(64channels)andQDMA

channels(8channels).

DMAchannels,atriggereventmaybeduetoanexternalevent,manual

writetotheeventtregister,Achannels,it’s

maybeawritetotheur-programmedtriggerevent.

3)Besides,DMAchannelshashigherprioritythantheQDMAchannels,and

thelowest-numberedchannelisthehighestpriority.

4)EDMA3TCisresponsiblefordatamovement.

3、AnEDMA3transferisalwaysdefinedintermsofthree

dimensions(ACNT,BCNT,CCNT),whichonlysupportstwosynchronization

typesincludingA-synchronizedtransfers&AB--synchronizedtransfers.

1)ForA-synchronizedtransfer,eachevent/RTpacketconveysthetransfer

,BCNT*CCNTeventsareneededto

heframeixhausted,theaddressis

updatedbyaddingSRCCIDX/DSTCIDXtothebeginningaddressofthelast

arrayintheframe.

2)ForAB--synchronizedtransfers,eachevent/RTpacketconveysthetransfer

,

he

frameixhausted,theaddressisupdatedbyaddingSRCCIDX/DSTCIDX

tothebeginningaddressofthebeginningarrayintheframe.

4、rethreeeventqueues(Q0,Q1,Q2)for

DM643device,theysubmitTRs(transferrequests)toTC0,TC1,TC2

respectly.

1)EacheventqueueisrvicedinaFIFOorder,andalowernumberedqueue

hasahigherdequeuingprioritythanahighernumberedqueue.

2)Wecangettheevententriesbyaccessingtheevententryregisters(Q0E0to

Q2E15)whichcontainsthetypeofevent(manualevent,chainedor

autotriggered)andtheeventnumber.

3)Theprioritiesoftransferrequestsareprogrammedusingthequeueproirity

register(QUEPRI).

4)Whenaneventreashestheheadofthequeue,thePaRAMassociatedwith

thatchannelisreadtodeterminethetransferdetails.

5、EachPaRAMtincludeight4-bytesPaRAMtentries(32-bytestotalper

PaRAMt).

1)ThePaRAMstructuresupportsping-pong,circularbuffering,channel

chaining,andautoreloading(lingking).

2)AnullPaRAMtisdefinedasaPaRAMtwhereallcount

fileds(ACNT,BCNT,CCNT)ca,thebits

correspondingtothechannelistintheeventmissingregister(EMR,

EMRH,orQEMR)andcondaryeventregister(SER,SERH,QSER),therefor,

anyfutureeventonthischannelisignored,thisisanerrorcondition,andyou

mustclearthebitinSER,SERH,QSER.

3)AdummyPaRAMtisdefinedasaPaRAMtwhereatleastonecount

fileds(ACNT,BCNT,CCNT)isclearedto0andatleastonecount

fileds(ACNT,BCNT,CCNT)ca,itwillnottthebitin

EMR,EMRH,orQEMR,andwillclearthebitintheSER,SERH,

notanerrorcondition.

4)Parametertuodates:fornonfinalevent,thisincludesaddressandcount

updates,forfinalevent,-synchronized,

thisincudesBCNT,CCNT,SRC,-synchronized,thisincudes

CCNT,SRC,DST.

5)LinkingtransferonlyoccurswhentheSTATICbitinOPTisclearedto0.

whenthecurrentPaRAMteventparametershavebeenexhausted,itreloads

lsouasingle

QDMAchannelandmultiplePaRAMtstocreatealinkedlistoftransfer.

6)link-to-lf

6、TherearethreewaystheEDMA3CCgetsinformedaboutatransfercompletion:

1)normalcompletion,whentheEDMA3CCreceivestheTCCfromthe

EDMA3TC.

2)earlycompletion,.WhentheEDMA3CCsubmitstheTRtotheEDMA3TC.

3)anddummy/nullcompletion,

7、ThemappingbetweentheDMAchannelnumbersandthePaRAMtsisfixed.

ThemappingbetweentheQDMAchannelnumbersandthePaRAMtsis

programmbaleusingQDMAchannenmappingregister(QCHMAPn).

8、ldmakea

uniqueassignmentofQDMA/DMAcgannelstoagivenregion.

9、ChiningEDMA3channels:itallowsthecompletionofanEDMA3channel

transfertotrigeranotherEDMA3channeltransfer.

1)thedifferencebetweenlinkandchaining:linkreloadsthecunrrentchannel

parametertwiththelinkedparmetert,whilechainingprovidesa

synchronizatoneventtothechainedchannel.

2)therearethreetypes:finaltransfercompletionchaning,intermediatetransfer

completionchaning,bothfinalandintermediatetransfercompletionchaning

10、EDMA3interrupts:transfercompletioninterrupts&errorinterrupts.

1)transfercompletioninterrupts:TheEDMA3generatesasinglecompletion

ueis

directlymappedtothebitsofthe(interruptpendingregister)IPR/IPRH.

Besides,TCCcanbeprogrammedtoanyvalueforaDMA/QDMAchannel.

2)forenablingtransfercompletioninterrrupts,weshouldtIER/IERH,

IPR/IPRH,andifintheshadowregion,weshouldalsotDRAE/DRAEH.

3)forclearingtransfercompletioninterrrupts,wecanwritea1tothe

correspondingbitintheinterruptpendingclearregister(ICR/ICRH).

4)TheEDMA3CChasinterruptevaluateregisters(IEVAL)ineachshadow

EVALaretheonlyregistersthatarenotaffectedbythe

SRAE/of1totheEVALbitinIEVALwillresultinpulsing

theassociatedregioninterrupt,whichassuresthattheinteruptssrenotmisd

bytheCPU.

5)TheEDMA3CChasanerrorevaluateregisters(EEVAL)inglobalregion.A

writeof1totheEVALbitinEEVALwillresultinpulsingtheerrorinterrupt.

6)errorinterrupts:therearefourconditionscausingtheerrorinterruptstobe

pauld,includinga)DMAmisdeventforall64DMAchannels,which

getlatchedintheeventmisdregisters(EMR/EMRH).b)QDMAmisd

eventsforallQDMAchannels,whichgetlatchedintheQDMAeventmisd

register(QEMR).c)threshodexceedforalleventqueues,whichgetlatchedin

theEDMA3CCerrorregister(CCERR).d)TCCerrorforoutstandingtransfer

requestxceedingthemaximumlimitof63.

11、wecanutheeventqueueentryregister(QxEx)whichidenfiesthespecific

eventtype&eventnumberandthequeuestatusregister(QSTATn)which

includesstartpointer(STRTPTR)&thetotalnumberofvalidentries

(NUMVAL)toreadallevententries.

12、wecantrackqueueresourcebyreadingthequeuewatermarkthresholdA

register(QWAMTHRA)includingthresholdvalue(0~15),thequeuestaus

register(QSTATn)includingthemaximumqueueusageinthewatermark

(WM)ueueusageixceeded,wecan

knowitbyreadingtheQTHRXCDnbitinthechannelcontrollererror

register(CCERR)andtheTHRXCDbitintheQSTATn.

13、performancetuning:wecantreadcommandrateregister(RDRATE)which

definesthenumberofcyclesthattheEDMA3TCreadcontrollerwaitsbefore

ritesalwayshavean

intervalbetweencommands.

14、wecanutheDMAprogramregistert,DMAsourceactiveregistert,and

thedestinationFIFOregisterttoderiveabriefhistoryofTrsrviced

swecanknowtheongoingactivityin

differentpartsofthetransfercontrollerbyreadingEDMA3TCstatusregister

(TCSTAT)whichincludesSRCACTVbitindicatingwhetherthesource

activetisactive,DSTACTVbitindicatingthenumberofTRsresidentin

thedestinationregisteractivet,andPROGBUSYbitindicatingwhethera

validTRisprentintheDMApragramt.

15、thedestinationFIFOregisterpointerisimplementedasacircularbufferwith

thestartpointerbeingDFSTRPTRandabufferdepthofusually2or4.

16、whenconfiguringtheEDMA3TC,theDBSforeachtransfercontralleris

confugurablebyasystemmoduleregister(EDMATCCFG)to16,32,or64

bytes.

17、tirggersourcepriority:eventtrigger(viaER)ishigherprioritythanchain

trigger(viaCER)andchaintriggerishigherprioritythanmanualtrigger(via

ESR).

18、theEDMA3channelcontrollerandtransfercontrollerareclockedfromPLL1.

643,thisis

153MHZinnormalmode(DSPoperatingat459MHZ)or198MHZinturbo

mode(594MHZ).

19、powermanagement:theEDMA3controllercanbeidledonreceivingaclock

stoprequestfromthePSC,andtherequesttoEDMA3CCandEDMA3TC

doingthis,wecangetconditionsbyreadingthechannel

controllerstatusregister(CCSTAT)andTCSTAT.

1)whenputtingtheEDMA3controllerinreduced-powermodes,wehadbetter

firstdisabletheEDMA3CCandthentheEDMA3TCs.

2)ifESMA3isrvicingaperipheral,wehadbetterfirstdiasbletheperipheral,

thendisabletheDMAchannelassociatedwiththeperipheral,thendisablethe

EDMA3CC,andfinallydisabletheEDMA3TCs.

20、nonburstingperipheralincludestheon-chipmultichannelbufferedrial

port(McBSP).TheMcBSPtransmitandreceivedatastreamsaretreated

thecorrespondingDMAchannelshouldbeprogrammedtobeonqueue0.

21、burstingperipheral: