FPGA可编程逻辑器件芯片XC3S2000-4FGG456C中文规格书

Section II: Hardware Architecture

Chapter 10: Device I/O Connectivity

Chapter 10

Device I/O Connectivity

The Versal™ ACAP includes many different types of I/O pins. Each pin has a dedicated I/O buffer

with characteristics that are often programmable. The functionality of a pin can be dedicated to a

specific function or have a flexible assignment.

The I/O functionality and buffers for the PMC, PS, and other subsystems are summarized in the

following table. More information can be found in the TRM and online. The voltage banks for the

PMC and PS banks are listed in the Power Pins table. The voltage banks for the PL are listed in

the Versal ACAP Packaging and Pinouts Architecture Manual (AM013).

Table 4: PMC, PS, and Other I/O Buffer Pin Banks

Bank Name

PMC DIO Bank15PSIO

PMC DIO_A Bank4Analog

PMC MIO Bank 0

PMC MIO Bank 1

LPD MIO Bank26PSIO

XPIPE GTY16GTY

Pin

Count

52PSIO

Buffer TypeDescription

Dedicated I/O with POR_B, REF_CLK, JTAG, and boot mode.

Dedicated analog I/O pins: VREF, Analog-In.

See PMC Dedicated Pins.

Multiplexed I/O for boot devices and peripherals in the

PMC and LPD IOPs. See Multiplexed I/O Pins

and MIO

PSIO Buffer Configuration.

Usage table shown in XPIPE GTY Transceiver Channels.

Connections shown in Host Debug Ports.

Normally ud by DDRMC, available to PL fabric.

The XP IOL and IOB resources are described in the Versal

ACAP SelectIO Resources Architecture Manual (AM010).

Multiple banks of HDIO buffers connect PL to device pins.

The HDIO IOL and IOB resources are described in the

Versal ACAP SelectIO Resources Architecture Manual (AM010).

Listed in the Versal AI Core Series Data Sheet: DC and AC

Switching Characteristics (DS957).

Versal ACAP GTY Transceivers Architecture Manual (AM002).GTYxGTY

PL XPIOXP IOB

54 per

bank

PL HDIOxHD IOB

GTMxGTM

Related Information

Signals, Interfaces, Pins, and Controls

AM011 (v1.1) November 30, 2020

Versal ACAP TRM

Section II: Hardware Architecture

Chapter 10: Device I/O Connectivity

Device-Level Diagram

The device-level I/O connectivity is shown in the following figure.

Figure 11: I/O Connectivity Diagram

FPD

4x PSIO

Banks

503

XPipe

PL

PMC

Dedicated Signals

SYSMON

JTAG

DAP

P

S

I

O

PMC DIO Bank

PMC DIO_A

15

CPM4

CCIX

up to x8

up to x16

PCIe 1

PCIe 0

analog

500

A

6

P

S

I

O

PMC MIO Bank 0

PMC MIO Bank 1

IOP/Flash

26

26

16

HSDP

DMA

4x Quad

Banks

501

MIO

Mux

SBI

Trace

Flash

P

S

I

O

DPC

PL GTY for CPM4

SoC GTY for CPM5

HSDP

Aurora

x1

502

P

S

I

O

LPD MIO Bank

26

MIO

Mux

IOP

MIO

LPD

EMIO

DDR Memory

Controller

BLI

DRAM

or PL

PL

H

D

I

O

PL I/O

Building

Blocks

Block RAM

UltraRAM

Integrated Peripherals

100G Ethernet MRMAC

600G Ethernet channel

600G Interlaken

400G HSCE

G

T

M

PMC

PL

LPD

SPD

DSP Engine

Clocks

G

T

Y

Power Domains

CLB

X

P

I

O

X22413-111220

AM011 (v1.1) November 30, 2020

Versal ACAP TRM

Section II: Hardware Architecture

Chapter 10: Device I/O Connectivity

PSIO Banks

The PSIO banks provide I/O connectivity for the PMC and LPD. Each bank includes LVCMOS

buffers with veral programmable features. There are four PSIO banks. Three banks are for the

multiplexed I/O (MIO) and one bank is for the PMC dedicated pins.

There are also four dedicated analog signals (DIO_A) associated with the system monitor

(SYSMON).

•Bank 500:

○

PMC MIO bank 0 with 26 pins

PMC dedicated analog pins Versal ACAP System Monitor Architecture Manual (AM006)

○

•Bank 501: PMC MIO bank 1 with 26 pins

•Bank 502: LPD MIO bank with 26 pins

•Bank 503: PMC dedicated digital with 15 pins

The PMC and LPD MIO pins are described in the Multiplexed I/O Pins chapter. The dedicated

pins are described in the PMC Dedicated Pins chapter.

XPIPE GTY Transceiver Channels

The XPIPE GTY transceivers are assigned to the high-speed interface controllers in the CPM, PS,

and PL.

•PCIe controller 0 in CPM

®

•PCIe controller 1 in CPM

•High-speed debug port, HSDP in PS

•PL fabric

Sixteen transceivers are grouped into four quad banks. All four channels within a quad are

assigned to the same interface. If the interface does not require all four channels, then there are

unud channels within that quad. The combination of interfaces that can u the GTY

transceivers are summarized in the table below; the HSDP is reprented by 'HS'.

The connections to the XPipe and GTY transceivers are illustrated in High-Speed Debug Port

ction of the Integrated Debug chapter.

AM011 (v1.1) November 30, 2020

Versal ACAP TRM